The 29th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, January 22, 2024

Room 204	Room 205	Room 206	Room 207
T1 Tutorial to NeuroSim: A Versatile Benchmark Framework for AI Hardware 9:30 - 12:30	T2 Toward Robust Neural Network Computation on Emerging Crossbar-based Hardware and Digital Systems 9:30 - 12:30	T3 Morpher: A Compiler and Simulator Framework for CGRA 9:30 - 12:30	T4 Machine Learning for Computational Lithography 9:30 - 12:30
Lunch 12:30 - 14:00
T5 Low Power Design: Current Practice and Opportunities 14:00 - 17:00	T6 Leading the industry, Samsung CXL Technology 14:00 - 17:00	T7 Sparse Acceleration for Artificial Intelligence: Progress and Trends 14:00 - 17:00	T8 CircuitOps and OpenROAD: Unleashing ML EDA for Research and Education 14:00 - 17:00

Tuesday, January 23, 2024

Room 204	Room 205	Room 206	Room 207	Room 107/108	Room 110/111
1K (Room Premier A/B) Opening and Keynote Session I 9:00 - 10:30
Coffee Break 10:30 - 10:45
1A Emerging NoC Designs 10:45 - 12:00	1B When AI Meets Edge Devices 10:45 - 12:00	1C Innovations in New Computing Paradigms: Stochastic, Hyper-Dimensional and High-Performance Computing 10:45 - 12:00	1D 3D IC 10:45 - 12:00	1E (SS-1) Open-Source EDA Algorithms and Software 10:45 - 12:25	1F (DF-4) Advanced EDA using AI/ML at Synopsys 10:45 - 11:45
2A Frontiers in Embedded and Edge AI: from Adversarial Attacks to Intelligent Homes 13:30 - 14:45	2B Innovations in Quantum EDA: from Design to Deployment 13:30 - 15:10	2C Architecting for Dependability: System Design with Compute-in-Memory 13:30 - 15:10	2D ML for Physical Design and Timing 13:30 - 15:10	2E University Design Contest 13:30 - 15:20	2F (DF-1) Next-Generation AI Semiconductor Design 13:30 - 15:10
3A GPU and Custom Accelerators 15:30 - 17:35	3B Hardware Acceleration for Graph Neural Networks and New Models 15:30 - 17:35	3C New Frontiers in Verification and Simulation 15:30 - 17:35	3D Partition and Placement 15:30 - 17:35	3E (SS-2) Hardware Security -- A True Multidisciplinary Research Area 15:30 - 17:35	3F (DF-2) Heterogeneous Integration and Chiplet Design 15:30 - 17:10
1S (Room 204/205) SIGDA Student Research Forum 18:00 - 21:00

Wednesday, January 24, 2024

Room 204	Room 205	Room 206	Room 207	Room 107/108
4A Detection Techniques for SoC Vulnerability and Malware 9:00 - 10:15	4B Design for Manufacturability: from Rule Checking to Yield Optimization 9:00 - 10:15	4C Advances in Logic Synthesis and Optimization 9:00 - 10:15	4D Learning-Based Optimization for RF/Analog Circuit 9:00 - 10:15	4E (SS-3) LLM Acceleration and Specialization for Circuit Design and Edge Applications 8:35 - 10:15
2K (Room Premier A/B) Keynote Session II 10:30 - 11:30
5A Bridging Memory, Storage, and Data Processing Techniques 13:00 - 14:40	5B Exploring EDA’s Next Frontier: AI-Driven Innovative Design Methods 13:00 - 14:40	5C New Frontiers in Testing 13:00 - 14:40	5D FPGA-Based Neural Network Accelerator Designs and Applications 13:00 - 14:40	5E (DF-3) AI/ML for Chip Design and EDA - Current Status and Future Perspectives from Diverse Views 13:00 - 14:40
6A Enabling Techniques to Make CIM Small and Flexible 15:00 - 16:40	6B Emerging Trends in Hardware Design: from Biochips to Quantum Systems 15:00 - 17:05	6C New Advances in Logic Locking and Side-Channel Analysis 15:00 - 17:05	6D Advanced Simulation and Modeling 15:00 - 17:05	6E (SS-4) Cutting-Edge Techniques for EDA in Analog/Mixed-Signal ICs 15:00 - 16:40
Banquet (Grand Ballroom A/B) 18:00 - 19:30
CEDA activity (Grand Ballroom A/B) 18:00 - 18:15
3K (Grand Ballroom A/B) Keynote Session III 18:15 - 19:15

Thursday, January 25, 2024

Room 204	Room 205	Room 206	Room 207	Room 107/108
7A System Performance and Debugging 9:00 - 10:15	7B Innovations in Autonomous Systems: Hyperdimensional Computing and Emerging Application Frontiers 9:00 - 10:15	7C Productivity Management for High Level Design 9:00 - 10:15	7D Emerging Memory Yield Optimization and Modeling 9:00 - 10:15	7E (SS-5) Enabling Chiplet-based Custom Designs 8:35 - 10:15
4K (Room Premier A/B) Keynote Session IV 10:30 - 11:30
8A Advances in Efficient Embedded Computing: from Hardware Accelerator to Task Management 13:00 - 14:40	8B In-Memory Computing Architecture Design and Logic Synthesis 13:00 - 14:40	8C Firing Less for Evolution: Quantization & Learning Spikes 13:00 - 14:40	8D New Techniques for Photonics and Analog Circuit Design 13:00 - 14:40	8E (JW-1) TILOS & AI-EDA Joint Workshop - I 13:00 - 14:40
9A Advancing AI Algorithms: Faster, Smarter, and More Efficient 15:00 - 16:40	9B Design Explorations for Neural Network Accelerators 15:00 - 17:05	9C High-Level Security Verification and Efficient Implementation 15:00 - 17:05	9D Routing 15:00 - 16:15	9E (JW-2) TILOS & AI-EDA Joint Workshop - II 15:00 - 16:40

DF: Designers' Forum, SS: Special Session

List of papers

Remark: The presenter of each paper is marked with "*".

Monday, January 22, 2024

[To Session Table]

Session T1 Tutorial to NeuroSim: A Versatile Benchmark Framework for AI Hardware
Time: 9:30 - 12:30, Monday, January 22, 2024
Location: Room 204
Chair: Shimeng Yu (Georgia Tech, USA)

T1-1

Title	(Tutorial) Tutorial to NeuroSim: A Versatile Benchmark Framework for AI Hardware
Author	Shimeng Yu (Georgia Tech, USA)
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session T2 Toward Robust Neural Network Computation on Emerging Crossbar-based Hardware and Digital Systems
Time: 9:30 - 12:30, Monday, January 22, 2024
Location: Room 205
Chair: Masanori Hashimoto (Kyoto Univ., Japan)

T2-1

Title	(Tutorial) Toward Robust Neural Network Computation on Emerging Crossbar-based Hardware and Digital Systems
Author	Yiyu Shi (Univ. of Notre Dame, USA), Masanori Hashimoto (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session T3 Morpher: A Compiler and Simulator Framework for CGRA
Time: 9:30 - 12:30, Monday, January 22, 2024
Location: Room 206
Chair: Tulika Mitra (National Univ. of Singapore, Singapore)

T3-1

Title	(Tutorial) Morpher: A Compiler and Simulator Framework for CGRA
Author	Tulika Mitra, Zhaoying Li, Thilini Kaushalya Bandara (National Univ. of Singapore, Singapore)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T4 Machine Learning for Computational Lithography
Time: 9:30 - 12:30, Monday, January 22, 2024
Location: Room 207
Chair: Yonghwi Kwon (Synopsys, USA)

T4-1

Title	(Tutorial) Machine Learning for Computational Lithography
Author	Yonghwi Kwon (Synopsys, USA), Haoyu Yang (NVIDIA Research, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T5 Low Power Design: Current Practice and Opportunities
Time: 14:00 - 17:00, Monday, January 22, 2024
Location: Room 204
Chair: Gang Qu (Univ. of Maryland, USA)

T5-1

Title	(Tutorial) Low Power Design: Current Practice and Opportunities
Author	Gang Qu (Univ. of Maryland, USA)
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session T6 Leading the industry, Samsung CXL Technology
Time: 14:00 - 17:00, Monday, January 22, 2024
Location: Room 205
Chair: Jeongheyon Cho (Samsung Electronics, Republic of Korea)

T6-1

Title	(Tutorial) Leading the industry, Samsung CXL Technology
Author	Jeonghyeon Cho, Jinin So, Kyungsan Kim (Samsung Electronics, Republic of Korea)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T7 Sparse Acceleration for Artificial Intelligence: Progress and Trends
Time: 14:00 - 17:00, Monday, January 22, 2024
Location: Room 206
Chair: Guohao Dai (Shanghai Jiao Tong Univ., China)

T7-1

Title	(Tutorial) Sparse Acceleration for Artificial Intelligence: Progress and Trends
Author	Guohao Dai (Shanghai Jiao Tong Univ., China), Xiaoming Chen (Chinese Academy of Sciences, China), Mingyu Gao, Zhenhua Zhu (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T8 CircuitOps and OpenROAD: Unleashing ML EDA for Research and Education
Time: 14:00 - 17:00, Monday, January 22, 2024
Location: Room 207
Chair: Andrew B. Kahng (Synopsys, USA)

T8-1

Title	(Tutorial) CircuitOps and OpenROAD: Unleashing ML EDA for Research and Education
Author	Andrew B. Kahng (Univ. of California San Diego, USA), Vidya A. Chhabria (Arizona State Univ., USA)
Detailed information (abstract, keywords, etc)

Tuesday, January 23, 2024

[To Session Table]

Session 1K Opening and Keynote Session I
Time: 9:00 - 10:30, Tuesday, January 23, 2024
Location: Room Premier A/B
Chairs: Kyu-Myung Choi (Seoul National Univ., Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea)

1K-1

Title	ASP-DAC 2024 Opening
Detailed information

1K-2

Title	(Keynote Address) Advanced Technology and Design Enablement
Author	Sei Seung Yoon (Samsung Electronics, Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session 1A Emerging NoC Designs
Time: 10:45 - 12:00, Tuesday, January 23, 2024
Location: Room 204
Chair: Qinru Qiu (Syracuse Univ., USA)

1A-1 (Time: 10:45 - 11:10)

Title	CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs
Author	*Tom Glint (IIT Gandhinagar, India), Manu Awasthi (Ashoka Univ., India), Joycee Mekie (IIT Gandhinagar, India)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 11:10 - 11:35)

Title	PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoC
Author	*Zifeng Zhao, Xinghao Zhu, Jiyuan Bai, Gengsheng Chen (Fudan Univ., China)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)
Slides

1A-3 (Time: 11:35 - 12:00)

Title	SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating
Author	*Fan Jiang, Chengeng Li, Lin Chen, Jiaqi Liu, Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1B When AI Meets Edge Devices
Time: 10:45 - 12:00, Tuesday, January 23, 2024
Location: Room 205
Chairs: Guangyu Sun (Peking Univ., China), Jinjun Xiong (Univ. at Buffalo, USA)

Best Paper Candidate
1B-1 (Time: 10:45 - 11:10)

Title	QuadraNet: Improving High-Order Neural Interaction Efficiency with Hardware-Aware Quadratic Neural Networks
Author	*Chenhui Xu, Fuxun Yu, Zirui Xu (George Mason Univ., USA), Chenchen Liu (Univ. of Maryland, Baltimore County, USA), Jinjun Xiong (Univ. at Buffalo, USA), Xiang Chen (George Mason Univ., USA)
Page	pp. 19 - 25
Detailed information (abstract, keywords, etc)
Slides

1B-2 (Time: 11:10 - 11:35)

Title	RobustDiCE: Robust and Distributed CNN Inference at the Edge
Author	*Xiaotian Guo (Univ. of Amsterdam/Leiden Univ., Netherlands), Quan Jiang (Nanjing Agricultural Univ., China), Andy Pimentel (Univ. of Amsterdam, Netherlands), Todor Stefanov (Leiden Univ., Netherlands)
Page	pp. 26 - 31
Detailed information (abstract, keywords, etc)
Slides

1B-3 (Time: 11:35 - 12:00)

Title	YoseUe: "trimming" Random Forest's training towards resource-constrained inference
Author	*Alessandro Verosimile, Alessandro Tierno, Andrea Damiani, Marco Domenico Santambrogio (Politecnico di Milano, Italy)
Page	pp. 32 - 37
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1C Innovations in New Computing Paradigms: Stochastic, Hyper-Dimensional and High-Performance Computing
Time: 10:45 - 12:00, Tuesday, January 23, 2024
Location: Room 206
Chair: Yue Zhang (Beihang Univ., China)

1C-1 (Time: 10:45 - 11:10)

Title	P2LSG: Powers-of-2 Low-Discrepancy Sequence Generator for Stochastic Computing
Author	Mehran Shoushtari Moghadam, Sercan Aygun, Mohsen Riahi Alam, *M Hassan Najafi (Univ. of Louisiana, Lafayette, USA)
Page	pp. 38 - 45
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 11:10 - 11:35)

Title	PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing
Author	*Fangxin Liu, Haomin Li, Ning Yang (Shanghai Jiao Tong Univ., China), Yichi Chen (Tianjin Univ., China), Zongwu Wang (Shanghai Jiao Tong Univ., China), Tao Yang (Huawei Technologies, China), Li Jiang (Shanghai Jiao Tong Univ., China)
Page	pp. 46 - 51
Detailed information (abstract, keywords, etc)
Slides

1C-3 (Time: 11:35 - 12:00)

Title	FPGA-Based HPC for Associative Memory System
Author	*Deyu Wang (Fudan Univ., China), Yuning Wang (Univ. of Turku, Finland), Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner (Royal Inst. of Tech., Sweden), Jiawei Xu (Guangdong Institute of Intelligence Science and Technology, China), Li-Rong Zheng, Zhuo Zou (Fudan Univ., China)
Page	pp. 52 - 57
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1D 3D IC
Time: 10:45 - 12:00, Tuesday, January 23, 2024
Location: Room 207
Chairs: Sunmean Kim (Kyungpook National Univ., Republic of Korea), Daijoon Hyun (Cheong-Ju Univ., Republic of Korea)

1D-1 (Time: 10:45 - 11:10)

Title	Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration
Author	*Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 58 - 64
Detailed information (abstract, keywords, etc)

Best Paper Candidate
1D-2 (Time: 11:10 - 11:35)

Title	CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs
Author	*Bangqi Fu, Lixin Liu, Yang Sun, Wing-Ho Lau, Martin D.F. Wong, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 65 - 70
Detailed information (abstract, keywords, etc)
Slides

1D-3 (Time: 11:35 - 12:00)

Title	O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs
Author	*Xingyu Tong, Zhijie Cai, Peng Zou, Min Wei, Yuan Wen (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China)
Page	pp. 71 - 76
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1E (SS-1) Open-Source EDA Algorithms and Software
Time: 10:45 - 12:25, Tuesday, January 23, 2024
Location: Room 107/108
Chairs: Qi Sun (Zhejiang Univ.), Ting-Chi Wang (National Tsing-Hua Univ.)

1E-1 (Time: 10:45 - 11:10)

Title	(Invited Paper) iEDA: An Open-source infrastructure of EDA
Author	*Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang (Peng Cheng Laboratory, China), Hao Wang (Chinese Academy of Sciences, China), Yifan Li (Peng Cheng Laboratory, China), Yihang Qiu (Univ. of Chinese Academy of Sciences, China), Guojie Luo (Peking Univ., China), Huawei Li (Chinese Academy of Sciences, China), Haihua Shen (Univ. of Chinese Academy of Sciences, China), Mingyu Chen, Dongbo Bu (Chinese Academy of Sciences, China), Wenxing Zhu (Fuzhou Univ., China), Ye Cai (Shenzhen Univ., Chile), Xiaoming Xiong (Guangdong Univ. of Tech., China), Ying Jiang, Yi Heng (Sun Yat-sen Univ., China), Peng Zhang (Peng Cheng Laboratory, China), Bei Yu (Chinese Univ. of Hong Kong, China), Biwei Xie, Yungang Bao (Chinese Academy of Sciences, China)
Page	pp. 77 - 82
Detailed information (abstract, keywords, etc)
Slides

1E-2 (Time: 11:10 - 11:35)

Title	(Invited Paper) iPD: An Open-source intelligent Physical Design Toolchain
Author	Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang (Peng Cheng Laboratory, China), Hongxi Wu (Fuzhou Univ., China), Weiguo Li (Minnan Normal Univ., China), Zengrong Huang, Liwei Ni (Peng Cheng Laboratory, China), Xueyan Zhao (Chinese Academy of Sciences, China), He Liu (Peking Univ., China), Shuaiying Long (Peng Cheng Laboratory, China), Ruizhi Liu (Chinese Academy of Sciences, China), Xiaoze Lin, Bo Yang (Peng Cheng Laboratory, China), Fuxing Huang (Fuzhou Univ., China), Zonglin Yang (Shenzhen Univ., China), Yihang Qiu (Univ. of Chinese Academy of Sciences, China), Zheqing Shao (Univ. of Science and Tech. of China, China), Jikang Liu, Yuyao Liang (Shenzhen Univ., China), Biwei Xie, Yungang Bao (Chinese Academy of Sciences, China), *Bei Yu (Chinese Univ. of Hong Kong, China)
Page	pp. 83 - 88
Detailed information (abstract, keywords, etc)
Slides

1E-3 (Time: 11:35 - 12:00)

Title	(Invited Paper) A Resource-efficient Task Scheduling System Using Reinforcement Learning
Author	Chedi Morchdi (Univ. of Utah, USA), Cheng-Hsiang Chiu (Univ. of Wisconsin at Madison, USA), Yi Zhou (Univ. of Utah, USA), *Tsung-Wei Huang (Univ. of Wisconsin at Madison, USA)
Page	pp. 89 - 95
Detailed information (abstract, keywords, etc)
Slides

1E-4 (Time: 12:00 - 12:25)

Title	(Invited Paper) Machine learning and GPU accelerated sparse linear solvers for transistor-level circuit simulation: a perspective survey
Author	*Zhou Jin, Wenhao Li, Yinuo Bai, Tengcheng Wang, Yicheng Lu, Weifeng Liu (China Univ. of Petroleum-Beijing, China)
Page	pp. 96 - 101
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1F (DF-4) Advanced EDA using AI/ML at Synopsys
Time: 10:45 - 11:45, Tuesday, January 23, 2024
Chair: Heechun Park (Kookmin Univ., Republic of Korea)

1F-1 (Time: 10:45 - 11:15)

Title	(Designers' Forum) AI-Driven Solution for DFT Optimization
Author	Soochang Park (EDA Group, Synopsys, USA)
Detailed information (abstract, etc)

1F-2 (Time: 11:15 - 11:45)

Title	(Designers' Forum) Optimization of PDN and DTCO using Synopsys Machine Learning Framework
Author	Kyoung-In Cho (EDA Group, Synopsys, USA)
Detailed information (abstract, etc)

[To Session Table]

Session 2A Frontiers in Embedded and Edge AI: from Adversarial Attacks to Intelligent Homes
Time: 13:30 - 14:45, Tuesday, January 23, 2024
Location: Room 204
Chair: BaekGyu Kim (Daegu Gyeongbuk Inst. of Science and Tech., Republic of Korea)

2A-1 (Time: 13:30 - 13:55)

Title	HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN
Author	*Zehua Yuan, Junhao Pan, Xiaofan Zhang, Deming Chen (Univ. of Illinois at Urbana Champaign, USA)
Page	pp. 102 - 108
Detailed information (abstract, keywords, etc)
Slides

2A-2 (Time: 13:55 - 14:20)

Title	Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge Platforms
Author	*Zain Taufique (Univ. of Turku, Finland), Antonio Miele (Politecnico di Milano, Italy), Pasi Liljeberg, Anil Kanduri (Univ. of Turku, Finland)
Page	pp. 109 - 114
Detailed information (abstract, keywords, etc)
Slides

2A-3 (Time: 14:20 - 14:45)

Title	Extending Neural Processing Unit and Compiler for Advanced Binarized Neural Networks
Author	Minjoon Song, Faaiz Asim, *Jongeun Lee (Ulsan National Inst. of Science and Tech. (UNIST), Republic of Korea)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2B Innovations in Quantum EDA: from Design to Deployment
Time: 13:30 - 15:10, Tuesday, January 23, 2024
Location: Room 205
Chair: Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong)

2B-1 (Time: 13:30 - 13:55)

Title	JustQ: Automated Deployment of Fair and Accurate Quantum Neural Networks
Author	Ruhan Wang, Fahiz Baba-Yara, *Fan Chen (Indiana Univ. Bloomington, USA)
Page	pp. 121 - 126
Detailed information (abstract, keywords, etc)

2B-2 (Time: 13:55 - 14:20)

Title	Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum Computers
Author	*Daniel Schönberger (Tech. Univ. of Munich, Germany), Stefan Hillmich (Software Competence Center Hagenberg (SCCH) GmbH, Austria), Matthias Brandl (Infineon Technologies AG, Germany), Robert Wille (Tech. Univ. of Munich, Germany)
Page	pp. 127 - 133
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:20 - 14:45)

Title	Optimizing Decision Diagrams for Measurements of Quantum Circuits
Author	*Ryosuke Matsuo (Osaka Univ., Japan), Rudy Raymond (IBM, Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan), Shin-ichi Minato (Kyoto Univ., Japan)
Page	pp. 134 - 139
Detailed information (abstract, keywords, etc)
Slides

2B-4 (Time: 14:45 - 15:10)

Title	CTQr: Control and Timing-Aware Qubit Routing
Author	*Ching-Yao Huang, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 140 - 145
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2C Architecting for Dependability: System Design with Compute-in-Memory
Time: 13:30 - 15:10, Tuesday, January 23, 2024
Location: Room 206
Chair: Po-Chun Huang (National Taipei Univ. of Tech., Taiwan)

2C-1 (Time: 13:30 - 13:55)

Title	BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators
Author	*Akul Malhotra, Chunguang Wang, Sumeet Kumar Gupta (Purdue Univ., USA)
Page	pp. 146 - 152
Detailed information (abstract, keywords, etc)
Slides

2C-2 (Time: 13:55 - 14:20)

Title	ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns
Author	*Yiming Chen, Guodong Yin, Hongtao Zhong, Mingyen Lee, Huazhong Yang (Tsinghua Univ., China), Sumitha George (North Dakota State Univ., USA), Vijaykrishnan Narayanan (Pennsylvania State Univ., USA), Xueqing Li (Tsinghua Univ., China)
Page	pp. 153 - 158
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 14:20 - 14:45)

Title	A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators
Author	*Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu (Georgia Tech, USA)
Page	pp. 159 - 164
Detailed information (abstract, keywords, etc)

2C-4 (Time: 14:45 - 15:10)

Title	Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits
Author	*Kunihiro Oshima (Kyoto Univ., Japan), Kazunori Kuribara (AIST, Japan), Takashi Sato (Kyoto Univ., Japan)
Page	pp. 165 - 170
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 2D ML for Physical Design and Timing
Time: 13:30 - 15:10, Tuesday, January 23, 2024
Location: Room 207
Chair: Pei-Yu Lee (Synopsys, Taiwan)

2D-1 (Time: 13:30 - 13:55)

Title	Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction
Author	*Xu Cheng, Yuyang Ye, Guoqing He, Qianqian Song, Peng Cao (Southeast Univ., China)
Page	pp. 171 - 176
Detailed information (abstract, keywords, etc)

2D-2 (Time: 13:55 - 14:20)

Title	An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning
Author	*Guoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao (Southeast Univ., China)
Page	pp. 177 - 182
Detailed information (abstract, keywords, etc)
Slides

2D-3 (Time: 14:20 - 14:45)

Title	BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization
Author	*Hang Wu, Ning Xu (Wuhan Univ. of Tech., China), Wei Xing, Yuanqing Cheng (Beihang Univ., China)
Page	pp. 183 - 188
Detailed information (abstract, keywords, etc)
Slides

2D-4 (Time: 14:45 - 15:10)

Title	Timing Analysis beyond Complementary CMOS Logic Styles
Author	*Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn (Univ. of Kaiserslautern-Landau, Germany), Sani Nassif (Radyalis LLC, USA)
Page	pp. 189 - 194
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2E University Design Contest
Time: 13:30 - 15:20, Tuesday, January 23, 2024
Location: Room 107/108
Chairs: Hyun Kim (Seoul National Univ. of Science and Tech., Republic of Korea), Ki-seok Chung (Hanyang Univ., Republic of Korea), Min-Seong Choo (Hanyang Univ., Republic of Korea), Jungwook Choi (Hanyang Univ., Republic of Korea)

2E-1 (Time: 13:30 - 13:40)

Title	An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network in 40nm CMOS
Author	*Sunghoon Kim, Wonjae Lee, Sundo Kim, Sungjin Park, Dongsuk Jeon (Seoul National Univ., Republic of Korea)
Page	pp. 195 - 196
Detailed information (abstract, keywords, etc)
Slides

2E-2 (Time: 13:40 - 13:50)

Title	A Mobile 3D-CNN Processor with Hierarchical Sparsity-Aware Computation and Temporal Redundancy-aware Network
Author	*Seungbin Kim, Kyuho Lee (Ulsan National Inst. of Science and Tech., Republic of Korea)
Page	pp. 197 - 198
Detailed information (abstract, keywords, etc)

2E-3 (Time: 13:50 - 14:00)

Title	A 740μW Real-Time Speech Enhancement Processor Using Band Optimization and Multiplier-Less PE Arrays for Hearing Assistive Devices
Author	*Sungjin Park, Sunwoo Lee (Seoul National Univ., Republic of Korea), Jeongwoo Park (Sungkyunkwan Univ., Republic of Korea), Hyeong-Seok Choi (Supertone, Republic of Korea), Dongsuk Jeon (Seoul National Univ., Republic of Korea)
Page	pp. 199 - 200
Detailed information (abstract, keywords, etc)

2E-4 (Time: 14:00 - 14:10)

Title	StrongARM Latch-based Clocked Comparator Design for Improving Low Speed DRAM Testing Reliability
Author	*Jongchan Lee, Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae (Kwangwoon Univ., Republic of Korea)
Page	pp. 201 - 202
Detailed information (abstract, keywords, etc)

2E-5 (Time: 14:10 - 14:20)

Title	Nano-Watt High-Resolution Continuous-Time Delta-Sigma Modulator With On-Chip PMIC for Sensor Applications
Author	*Jaedo Kim, Jiho Moon, Tian Guo, Chaeyoung Kang, Jeongjin Roh (Hanyang Univ., Republic of Korea)
Page	pp. 203 - 204
Detailed information (abstract, keywords, etc)
Slides

2E-6 (Time: 14:20 - 14:30)

Title	A 0.15-to-1.15V Output Range 270mA Self-Calibrating-Clocked Capacitor-Free LDO Using Rail-to-Rail Voltage-Difference-to-Time Converter with 0.183fs FoM
Author	*Youngmin Park, Dongsuk Jeon (Seoul National Univ., Republic of Korea)
Page	pp. 205 - 206
Detailed information (abstract, keywords, etc)

2E-7 (Time: 14:30 - 14:40)

Title	A 0.37 V 126 nW 0.29 mm2 65-nm CMOS Biofuel-Cell-Modulated Biosensing System Featuring an FSK-PIM-Combined 2.4 GHz Transmitter for Continuous Glucose Monitoring Contact Lenses
Author	Guowei Chen, Akiyoshi Tanaka (Nagoya Univ., Japan), *Kiichi Niitsu (Kyoto Univ., Japan)
Page	pp. 207 - 208
Detailed information (abstract, keywords, etc)

2E-8 (Time: 14:40 - 14:50)

Title	Power-Efficient FPGA Implementation of CNN-Based Object Detector
Author	*Haein Lee, Inseong Hwang, Hyun Kim (Seoul National Univ. of Science and Tech., Republic of Korea)
Page	pp. 209 - 210
Detailed information (abstract, keywords, etc)
Slides

2E-9 (Time: 14:50 - 15:00)

Title	TransCoder: Efficient Hardware Implementation of Transformer Encoder
Author	*Sangki Park, Chan-Hoon Kim, Soo-Min Rho, Jeong-Hyun Kim, Seo-Ho Chung, Ki-Seok Chung (Hanyang Univ., Republic of Korea)
Page	pp. 211 - 212
Detailed information (abstract, keywords, etc)
Slides

2E-10 (Time: 15:00 - 15:10)

Title	Implementation of a High-throughput and Accurate Gaussian-TinyYOLOv3 Hardware Accelerator
Author	*Juntae Park, Subin Ki, Hyun Kim (Seoul National Univ. of Science and Tech., Republic of Korea)
Page	pp. 213 - 214
Detailed information (abstract, keywords, etc)
Slides

2E-11 (Time: 15:10 - 15:20)

Title	A 17.01 MOP/s/LUT Binary Neural Network Inference Processor Showing 87.81% CIFAR10 Accuracy with 2.6M-bit On-Chip Parameters in a 28nm FPGA
Author	*Gil-Ho Kwak, Tae-Hwan Kim (Korea Aerospace Univ., Republic of Korea)
Page	pp. 215 - 216
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2F (DF-1) Next-Generation AI Semiconductor Design
Time: 13:30 - 15:10, Tuesday, January 23, 2024
Chair: Changho Han (Kumoh National Inst. of Tech., Republic of Korea)

2F-1 (Time: 13:30 - 13:55)

Title	(Designers' Forum) Building the programmable, high performance and energy-efficient AI chip for ChatGPT
Author	Joon Ho Baek (FuriosaAI, Republic of Korea)
Detailed information (abstract, keywords, etc)

2F-2 (Time: 13:55 - 14:20)

Title	(Designers' Forum) Enabling AI Innovation through Zero-touch SAPEON AI Inference System
Author	Soojung Ryu (SAPEON, Republic of Korea)
Detailed information (abstract, etc)

2F-3 (Time: 14:20 - 14:45)

Title	(Designers' Forum) Processing-in-Memory in Generative AI Era
Author	Kyomin Sohn (Samsung Electronics, Republic of Korea)
Detailed information (abstract, etc)

2F-4 (Time: 14:45 - 15:10)

Title	(Designers' Forum) AiMX: Cost-effective LLM accelerator using AiM (SK hynix’s PIM)
Author	Euicheol Lim (SK Hynix, Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session 3A GPU and Custom Accelerators
Time: 15:30 - 17:35, Tuesday, January 23, 2024
Location: Room 204
Chair: Tuo Li (Chinese Academy of Sciences, China)

3A-1 (Time: 15:30 - 15:55)

Title	Collaborative Coalescing of Redundant Memory Access for GPU System
Author	Fan Jiang, *Chengeng Li, Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China)
Page	pp. 217 - 222
Detailed information (abstract, keywords, etc)

3A-2 (Time: 15:55 - 16:20)

Title	WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR
Author	*En-Ming Huang, Bo-Wun Cheng (National Tsing Hua Univ., Taiwan), Meng-Hsien Lin (National Yang Ming Chiao Tung Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan), Tsung Tai Yeh (National Yang Ming Chiao Tung Univ., Taiwan)
Page	pp. 223 - 228
Detailed information (abstract, keywords, etc)
Slides

3A-3 (Time: 16:20 - 16:45)

Title	SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design
Author	*Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 229 - 234
Detailed information (abstract, keywords, etc)

3A-4 (Time: 16:45 - 17:10)

Title	ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning
Author	*Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi (Southeast Univ., China)
Page	pp. 235 - 240
Detailed information (abstract, keywords, etc)

3A-5 (Time: 17:10 - 17:35)

Title	Secco: Codesign for Resource Sharing in Regular-Expression Accelerators
Author	*Jackson Woodruff, Sam Ainsworth, Micahel F.P. O'Boyle (Univ. of Edinburgh, UK)
Page	pp. 241 - 246
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3B Hardware Acceleration for Graph Neural Networks and New Models
Time: 15:30 - 17:35, Tuesday, January 23, 2024
Location: Room 205
Chair: Mohamed M. Sabry Aly (Nanyang Technological Univ., Singapore)

Best Paper Candidate
3B-1 (Time: 15:30 - 15:55)

Title	SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration
Author	*Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing (Shanghai Jiao Tong Univ., China)
Page	pp. 247 - 252
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 15:55 - 16:20)

Title	APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction
Author	*Lei Dai (Chinese Academy of Sciences, China), Shengwen Liang, Ying Wang (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Zhongguancun National Laboratory, China), Huawei Li (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Peng Cheng Laboratory, China), Xiaowei Li (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Zhongguancun National Laboratory, China)
Page	pp. 253 - 259
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 16:20 - 16:45)

Title	FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds
Author	*Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng (Beihang Univ., China), Jin Dong (Beijing Academy of Blockchain and Edge Computing, China)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)
Slides

3B-4 (Time: 16:45 - 17:10)

Title	A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component Analysis
Author	*Yashwant Moses, Madhav Rao (International Institute of Information Technology Bangalore, India)
Page	pp. 266 - 271
Detailed information (abstract, keywords, etc)
Slides

3B-5 (Time: 17:10 - 17:35)

Title	Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting
Author	*Xiangzhong Luo (Nanyang Technological Univ., Singapore), Di Liu (Norwegian Univ. of Science and Tech., Norway), Hao Kong, Shuo Huai, Hui Chen, Shiqing Li, Guochu Xiong, Weichen Liu (Nanyang Technological Univ., Singapore)
Page	pp. 272 - 277
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3C New Frontiers in Verification and Simulation
Time: 15:30 - 17:35, Tuesday, January 23, 2024
Location: Room 206
Chair: Jaeyong Chung (Incheon National Univ., Republic of Korea)

Best Paper Candidate
3C-1 (Time: 15:30 - 15:55)

Title	On Decomposing Complex Test Cases for Efficient Post-silicon Validation
Author	Harshitha C, Sundarapalli Harikrishna, Peddakotla Rohith, *Sandeep Chandran (Indian Inst. of Tech. Palakkad, India), Rajshekar Kalayappan (Indian Inst. of Tech. Dharwad, India)
Page	pp. 278 - 283
Detailed information (abstract, keywords, etc)
Slides

3C-2 (Time: 15:55 - 16:20)

Title	DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction
Author	*Guangyu Hu, Jianheng Tang (Hong Kong Univ. of Science and Tech., Hong Kong), Changyuan Yu (Hong Kong Univ. of Science and Tech. (GZ), China), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Hongce Zhang (Hong Kong Univ. of Science and Tech. (GZ), China)
Page	pp. 284 - 290
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:20 - 16:45)

Title	TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
Author	*Yufeng Li, Yiwei Ci, Qiusong Yang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China)
Page	pp. 291 - 296
Detailed information (abstract, keywords, etc)
Slides

3C-4 (Time: 16:45 - 17:10)

Title	Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing
Author	*Christoph Hazott, Florian Stögmüller, Daniel Große (Johannes Kepler Univ. Linz, Austria)
Page	pp. 297 - 303
Detailed information (abstract, keywords, etc)
Slides

3C-5 (Time: 17:10 - 17:35)

Title	MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
Author	Simranjeet Singh (Indian Inst. of Tech. Bombay, India), Chandan Kumar Jha (Univ. of Bremen, Germany), Ankit Bende, Vikas Rana (Forschungszentrum Jülich GmbH, Germany), Sachin Parkar (Indian Inst. of Tech. Bombay, India), Rolf Drechsler (Univ. of Bremen, Germany), *Farhad Merchant (Newcastle Univ., Newcastle upon Tyne, UK)
Page	pp. 304 - 309
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3D Partition and Placement
Time: 15:30 - 17:35, Tuesday, January 23, 2024
Location: Room 207
Chair: Evangeline F. Y. (Young, Hong Kong)

3D-1 (Time: 15:30 - 15:55)

Title	An Effective Netlist Planning Approach for Double-sided Signal Routing
Author	*Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 310 - 315
Detailed information (abstract, keywords, etc)

3D-2 (Time: 15:55 - 16:20)

Title	An Analytical Placement Algorithm with Routing topology Optimization
Author	*Min Wei, Xingyu Tong, Zhijie Cai, Peng Zou (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China)
Page	pp. 316 - 321
Detailed information (abstract, keywords, etc)

3D-3 (Time: 16:20 - 16:45)

Title	Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs
Author	*Yuan Wen, Benchao Zhu (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China)
Page	pp. 322 - 327
Detailed information (abstract, keywords, etc)

3D-4 (Time: 16:45 - 17:10)

Title	Row Planning and Placement for Hybrid-Row-Height Designs
Author	*Ching-Yao Huang, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 328 - 333
Detailed information (abstract, keywords, etc)

3D-5 (Time: 17:10 - 17:35)

Title	TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design
Author	*Chen-Hao Hsu (Univ. of Texas, Austin, USA), Xiaoqing Xu, Hao Chen, Dino Ruic (X, USA), David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 334 - 340
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 3E (SS-2) Hardware Security -- A True Multidisciplinary Research Area
Time: 15:30 - 17:35, Tuesday, January 23, 2024
Location: Room 107/108
Chairs: Gang Qu (Univ. of Maryland College Park), Takashi Sato (Kyoto Univ.)

3E-1 (Time: 15:30 - 15:55)

Title	(Invited Paper) Towards Finding the Sources of Polymorphism in Polymorphic Gates
Author	Timothy Dunlap, Zelin Lu, *Gang Qu (Univ. of Maryland, USA)
Page	pp. 341 - 346
Detailed information (abstract, keywords, etc)

3E-2 (Time: 15:55 - 16:20)

Title	(Invited Paper) HOGE: Homomorphic Gate on An FPGA
Author	*Kotaro Matsuoka (Kyoto Univ., Japan), Song Bian (Beihang Univ., China), Takashi Sato (Kyoto Univ., Japan)
Page	pp. 347 - 354
Detailed information (abstract, keywords, etc)
Slides

3E-3 (Time: 16:20 - 16:45)

Title	(Invited Paper) Sensors for Remote Power Attacks: New Developments and Challenges
Author	*Brian Udugama (Univ. of New South Wales, Australia), Darshana Jayasinghe, Sri Parameswaran (Univ. of Sydney, Australia)
Page	pp. 355 - 362
Detailed information (abstract, keywords, etc)
Slides

3E-4 (Time: 16:45 - 17:10)

Title	(Invited Paper) PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage
Author	Yun-Shan Hsieh (Academia Sinica, Taiwan), Bo-Jun Chen (National Tsing Hua Univ., Taiwan), *Po-Chun Huang (National Taipei Univ. of Tech., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan)
Page	pp. 363 - 370
Detailed information (abstract, keywords, etc)

3E-5 (Time: 17:10 - 17:35)

Title	(Invited Paper) Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge
Author	Weimin Fu (Kansas State Univ., USA), Shijie Li, Yifang Zhao (Univ. of Science and Tech. of China, China), Haocheng Ma (Tianjin Univ., China), Raj Dutta (Silicon Assurance, USA), Xuan Zhang (Washington Univ. in St. Louis, USA), Kaichen Yang (Michigan Technological Univ., USA), *Yier Jin (Univ. of Science and Tech. of China, China), Xiaolong Guo (Kansas State Univ., USA)
Page	pp. 371 - 376
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3F (DF-2) Heterogeneous Integration and Chiplet Design
Time: 15:30 - 17:10, Tuesday, January 23, 2024
Organizer/Chair: Rino Choi (Inha Univ., Republic of Korea), Co-Chair: Jaeduk Han (Hanyang Univ., Republic of Korea)

3F-1 (Time: 15:30 - 15:55)

Title	(Designers' Forum) Co-Design Considerations of Heterogeneous Integrated Packaging
Author	Gu-Sung Kim (Kangnam Univ., Republic of Korea)
Detailed information (abstract, etc)

3F-2 (Time: 15:55 - 16:20)

Title	(Designers' Forum) Don’t Close Your Eyes on Temperature: System Level Thermal Perspectives of 3D Stacked Chips
Author	Sung Woo Chung (Korea Univ., Republic of Korea)
Detailed information (abstract, etc)

3F-3 (Time: 16:20 - 16:45)

Title	(Designers' Forum) Introducing UCIe: The Global Chiplet Interconnect Standard
Author	Youngbin Kwon (Samsung Electronics, Republic of Korea)
Detailed information (abstract, etc)

3F-4 (Time: 16:45 - 17:10)

Title	(Designers' Forum) Addressing Modeling and Simulation Challenges in Chiplet Interfaces
Author	Jaeha Kim (Seoul National Univ., Republic of Korea)
Detailed information (abstract, etc)

Wednesday, January 24, 2024

[To Session Table]

Session 4A Detection Techniques for SoC Vulnerability and Malware
Time: 9:00 - 10:15, Wednesday, January 24, 2024
Location: Room 204
Chair: Makoto Ikeda (Univ. of Tokyo, Japan)

4A-1 (Time: 9:00 - 9:25)

Title	FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection
Author	Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, *Mark Tehranipoor (Univ. of Florida, USA)
Page	pp. 377 - 383
Detailed information (abstract, keywords, etc)
Slides

4A-2 (Time: 9:25 - 9:50)

Title	DeepIncept: Diversify Performance Counters with Deep Learning to Detect Malware
Author	Zhuoran Li (Old Dominion Univ., USA), *Dan Zhao (Univ. of Arizona, USA)
Page	pp. 384 - 389
Detailed information (abstract, keywords, etc)

4A-3 (Time: 9:50 - 10:15)

Title	Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks
Author	*Sreenitha Kasarapu, Sanket Shukla, Sai Manoj PD (George Mason Univ., USA)
Page	pp. 390 - 395
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4B Design for Manufacturability: from Rule Checking to Yield Optimization
Time: 9:00 - 10:15, Wednesday, January 24, 2024
Location: Room 205
Chairs: Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Yuzhe Ma (Hong Kong Univ. of Science and Tech. (GZ), China)

4B-1 (Time: 9:00 - 9:25)

Title	APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level
Author	*Tao Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Haoyu Yang (Nvidia, USA), Kang Liu (Huazhong Univ. of Science and Tech., China), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 396 - 401
Detailed information (abstract, keywords, etc)
Slides

4B-2 (Time: 9:25 - 9:50)

Title	E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean Algorithms
Author	*Yifei Zhou, Zijian Wang, Chao Wang (Southeast Univ., China)
Page	pp. 402 - 407
Detailed information (abstract, keywords, etc)
Slides

4B-3 (Time: 9:50 - 10:15)

Title	CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits
Author	*Yanfang Liu (Beihang Univ., China), Wei Xing (Univ. of Sheffield, UK)
Page	pp. 408 - 413
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4C Advances in Logic Synthesis and Optimization
Time: 9:00 - 10:15, Wednesday, January 24, 2024
Location: Room 206
Chair: Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan)

Best Paper Award
4C-1 (Time: 9:00 - 9:25)

Title	FineMap: A Fine-grained GPU-parallel LUT Mapping Engine
Author	*Tianji Liu (Chinese Univ. of Hong Kong, Hong Kong), Lei Chen, Xing Li, Mingxuan Yuan (Huawei Noah's Ark Lab, Hong Kong SAR, Hong Kong), Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 414 - 419
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 9:25 - 9:50)

Title	Transduction Method for AIG Minimization
Author	*Yukio Miyasaka (UC Berkeley, USA)
Page	pp. 420 - 425
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 9:50 - 10:15)

Title	In Medio Stat Virtus: Combining Boolean and Pattern Matching
Author	Gianluca Radi, *Alessandro Tempia Calvino, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 426 - 432
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4D Learning-Based Optimization for RF/Analog Circuit
Time: 9:00 - 10:15, Wednesday, January 24, 2024
Location: Room 207
Chair: Hung-Ming Chen (National Yang Ming Chiao Tung Univ., Taiwan)

Best Paper Candidate
4D-1 (Time: 9:00 - 9:25)

Title	A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs
Author	*Hongjian Zhou (ShanghaiTech Univ., China), Yaguang Li (Texas A&M Univ., USA), Xin Xiong, Pingqiang Zhou (ShanghaiTech Univ., China)
Page	pp. 433 - 438
Detailed information (abstract, keywords, etc)

4D-2 (Time: 9:25 - 9:50)

Title	An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits
Author	*Zhikai Wang (Tsinghua Univ., China), Jingbo Zhou (Baidu Research, China), Xiaosen Liu, Yan Wang (Tsinghua Univ., China)
Page	pp. 439 - 444
Detailed information (abstract, keywords, etc)

4D-3 (Time: 9:50 - 10:15)

Title	MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier
Author	*Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng (Fudan Univ., China)
Page	pp. 445 - 450
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4E (SS-3) LLM Acceleration and Specialization for Circuit Design and Edge Applications
Time: 8:35 - 10:15, Wednesday, January 24, 2024
Location: Room 107/108
Chairs: Deming Chen (UIUC), Yao Chen (AUS)

4E-1 (Time: 8:35 - 9:00)

Title	(Invited Paper) Applications of LLM for Chip Design
Author	Haoxing (Mark) Ren (NVIDIA, USA)
Detailed information

4E-2 (Time: 9:00 - 9:25)

Title	(Invited Paper) TinyChat for On-device LLM
Author	Song Han (MIT, USA)
Detailed information

4E-3 (Time: 9:25 - 9:50)

Title	(Invited Paper) FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models
Author	Ruiyang Qin (Univ. of Notre Dame, USA), Yuting Hu (Univ. at Buffalo, USA), Zheyu Yan (Univ. of Notre Dame, USA), *Jinjun Xiong (Univ. at Buffalo, USA), Ahmed Abbasi, Yiyu Shi (Univ. of Notre Dame, USA)
Page	pp. 451 - 456
Detailed information (abstract, keywords, etc)

4E-4 (Time: 9:50 - 10:15)

Title	(Invited Paper) Software/Hardware Co-design for LLM and Its Application for Design Verification
Author	Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang (UIUC, USA), Xiaofan Zhang (Google, USA), *Deming Chen (UIUC, USA)
Page	pp. 457 - 463
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2K Keynote Session II
Time: 10:30 - 11:30, Wednesday, January 24, 2024
Location: Room Premier A/B
Chairs: Kyu-Myung Choi (Seoul National Univ., Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea)

2K-1

Title	(Keynote Address) Present and Future Challenges of High-Bandwidth Memory
Author	Myeong-Jae Park (SK Hynix, Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session 5A Bridging Memory, Storage, and Data Processing Techniques
Time: 13:00 - 14:40, Wednesday, January 24, 2024
Location: Room 204
Chair: Yuan-Hao Chang (Academia Sinica, Taiwan)

Best Paper Candidate
5A-1 (Time: 13:00 - 13:25)

Title	wearMeter: an Accurate Wear Metric for NAND Flash Memory
Author	*Min Ye (City Univ. of Hong Kong, Hong Kong), Qiao Li (Xiamen Univ., China), Daniel Wen (YEESTOR Microelectronics, China), Tei-Wei Kuo (National Taiwan Univ., Mohamed bin Zayed Univ. of Artificial Intelligence, Taiwan), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)
Page	pp. 464 - 469
Detailed information (abstract, keywords, etc)
Slides

5A-2 (Time: 13:25 - 13:50)

Title	Overlapping Aware Zone Allocation for LSM Tree-Based Store on ZNS SSDs
Author	*Jingcheng Shen, Lang Yang, Linbo Long, Renping Liu, Zhenhua Tan (Chongqing Univ. of Posts and Telecommunications, China), Congming Gao (Xiamen Univ., China), Yi Jiang (Chongqing Univ. of Posts and Telecommunications, China)
Page	pp. 470 - 475
Detailed information (abstract, keywords, etc)
Slides

5A-3 (Time: 13:50 - 14:15)

Title	Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data
Author	*Tom Glint (IIT Gandhinagar, India), Manu Awasthi (Ashoka Univ., India), Joycee Mekie (IIT Gandhinagar, India)
Page	pp. 476 - 481
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 14:15 - 14:40)

Title	Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture
Author	*Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing (Shanghai Jiao Tong Univ., China)
Page	pp. 482 - 487
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5B Exploring EDA’s Next Frontier: AI-Driven Innovative Design Methods
Time: 13:00 - 14:40, Wednesday, January 24, 2024
Location: Room 205
Chair: M. Hassan Najafi (Univ. of Louisiana, Lafayette, USA)

5B-1 (Time: 13:00 - 13:25)

Title	Variational Label-Correlation Enhancement for Congestion Prediction
Author	*Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang (Southeast Univ., China)
Page	pp. 488 - 493
Detailed information (abstract, keywords, etc)
Slides

5B-2 (Time: 13:25 - 13:50)

Title	Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks
Author	Tianliang Ma, Zhihui Deng, Xuguang Sun, *Leilai Shao (Shanghai Jiaotong Univ., China)
Page	pp. 494 - 499
Detailed information (abstract, keywords, etc)

5B-3 (Time: 13:50 - 14:15)

Title	Automated synthesis of mixed-signal ML inference hardware under accuracy constraints
Author	Kishor Kunal, Jitesh Poojary, S Ramprasath, Ramesh Harjani, *Sachin S. Sapatnekar (Univ. of Minnesota Twin Cities, USA)
Page	pp. 500 - 505
Detailed information (abstract, keywords, etc)
Slides

5B-4 (Time: 14:15 - 14:40)

Title	LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage
Author	*Hye Rim Ji, Jong Seong Kim, Jung Yun Choi (Samsung Electronics, Republic of Korea), Jee Hyong Lee (Sungkyunkwan Univ., Republic of Korea)
Page	pp. 506 - 512
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 5C New Frontiers in Testing
Time: 13:00 - 14:40, Wednesday, January 24, 2024
Location: Room 206
Chair: Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan)

5C-1 (Time: 13:00 - 13:25)

Title	QcAssert: Quantum Device Testing with Concurrent Assertions
Author	*Hasini Dilanka Witharana, Daniel Volya, Prabhat Mishra (Univ. of Florida, USA)
Page	pp. 513 - 518
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 13:25 - 13:50)

Title	HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation
Author	*Shruti Pandey, Jayadeva, Smruti R. Sarangi (Indian Inst. of Tech. Delhi, India)
Page	pp. 519 - 524
Detailed information (abstract, keywords, etc)
Slides

5C-3 (Time: 13:50 - 14:15)

Title	A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver
Author	*Zhiteng Chao (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Xindi Zhang (Univ. of Chinese Academy of Sciences/Chinese Academy of Sciences, China), Junying Huang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Jing Ye (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Shaowei Cai (Univ. of Chinese Academy of Sciences/Chinese Academy of Sciences, China), Huawei Li, Xiaowei Li (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China)
Page	pp. 525 - 530
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 14:15 - 14:40)

Title	A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures
Author	*Sina Bakhtavari Mamaghani, Priyanjana Pal, Mehdi Baradaran Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 531 - 536
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 5D FPGA-Based Neural Network Accelerator Designs and Applications
Time: 13:00 - 14:40, Wednesday, January 24, 2024
Location: Room 207
Chair: Fan Chen (Indiana Univ. Bloomington, USA)

5D-1 (Time: 13:00 - 13:25)

Title	SWAT: An Efficient Swin Transformer Accelerator Based on FPGA
Author	*Qiwei Dong, Xiaoru Xie, Zhongfeng Wang (Nanjing Univ., China)
Page	pp. 537 - 542
Detailed information (abstract, keywords, etc)
Slides

5D-2 (Time: 13:25 - 13:50)

Title	TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization
Author	*Hongji Wang, Yueyin Bai, Jun Yu, Kun Wang (Fudan Univ., China)
Page	pp. 543 - 548
Detailed information (abstract, keywords, etc)

5D-3 (Time: 13:50 - 14:15)

Title	Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier
Author	*Zihang Ma, Zeyu Li, Yuanfang Wang, Yu Li, Jun Yu, Kun Wang (Fudan Univ., China)
Page	pp. 549 - 554
Detailed information (abstract, keywords, etc)

5D-4 (Time: 14:15 - 14:40)

Title	ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots
Author	*Jinho Yang, Sungwoong Yune, Sukbin Lim, Donghyuk Kim, Joo-Young Kim (KAIST, Republic of Korea)
Page	pp. 555 - 560
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5E (DF-3) AI/ML for Chip Design and EDA - Current Status and Future Perspectives from Diverse Views
Time: 13:00 - 14:40, Wednesday, January 24, 2024
Location: Room 107/108
Organizer: Changho Han (Kumoh National Inst. of Tech., Republic of Korea), Chair: Kyumyung Choi (Seoul National Univ., Republic of Korea)

5E-1 (Time: 13:00 - 13:25)

Title	(Designers' Forum) AI for Chip Design & EDA: Everything, Everywhere, All at Once (?)
Author	David Pan (Univ. of Texas, Austin, USA)
Detailed information (abstract, etc)

5E-2 (Time: 13:25 - 13:50)

Title	(Designers' Forum) How Engineers can Leverage AI Solutions in Chip Design
Author	Erick Chao (Cadence Design Systems, Taiwan)
Detailed information (abstract, etc)

5E-3 (Time: 13:50 - 14:15)

Title	(Designers' Forum) AI/ML Empowered Semiconductor Memory Design: An Industry Vision
Author	Hyojin Choi (Samsung Electronics, Republic of Korea)
Detailed information (abstract, etc)

5E-4 (Time: 14:15 - 14:40)

Title	(Designers' Forum) ML for Computational Lithography: What Will Work and What Will Not?
Author	Youngsoo Shin (KAIST, Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session 6A Enabling Techniques to Make CIM Small and Flexible
Time: 15:00 - 16:40, Wednesday, January 24, 2024
Location: Room 204
Chair: Qiao Li (Xiamen Univ., China)

6A-1 (Time: 15:00 - 15:25)

Title	OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
Author	*Yung-Chin Chen (National Taiwan Univ./Keio Univ., Taiwan), Shimpei Ando, Daichi Fujiki (Keio Univ., Japan), Shinya Takamaeda-Yamazaki (Univ. of Tokyo, Japan), Kentaro Yoshioka (Keio Univ., Japan)
Page	pp. 561 - 566
Detailed information (abstract, keywords, etc)

6A-2 (Time: 15:25 - 15:50)

Title	BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator
Author	*Cheng-Yang Chang, Chi-Tse Huang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu (Andy) Wu (National Taiwan Univ., Taiwan)
Page	pp. 567 - 572
Detailed information (abstract, keywords, etc)
Slides

6A-3 (Time: 15:50 - 16:15)

Title	A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications
Author	*Lizhou Wu, Chenyang Zhao (Fudan Univ., China), Jingbo Wang (Tongji Univ., China), Xueru Yu, Shoumian Chen, Chen Li (Shanghai Integrated Circuits R&D Center, China), Jun Han, Xiaoyong Xue, Xiaoyang Zeng (Fudan Univ., China)
Page	pp. 573 - 578
Detailed information (abstract, keywords, etc)
Slides

6A-4 (Time: 16:15 - 16:40)

Title	PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning Transformers
Author	*Yue Pan, Minxuan Zhou (Univ. of California, San Diego, USA), Chonghan Lee, Zheyu Li, Rishika Kushwah, Vijaykrishnan Narayanan (Pennsylvania State Univ., USA), Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 579 - 585
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6B Emerging Trends in Hardware Design: from Biochips to Quantum Systems
Time: 15:00 - 17:05, Wednesday, January 24, 2024
Location: Room 205
Chair: Hiromitsu Awano (Kyoto Univ., Japan)

6B-1 (Time: 15:00 - 15:25)

Title	Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning
Author	*Huayang Cai, Genggeng Liu, Wenzhong Guo (Fuzhou Univ., China), Zipeng Li (Silicon Engineering Group, Apple, Cupertino, CA, USA), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Xing Huang (Northwestern Polytechnical Univ., China)
Page	pp. 586 - 591
Detailed information (abstract, keywords, etc)
Slides

6B-2 (Time: 15:25 - 15:50)

Title	Towards Automated Testing of Multiplexers in Fully Programmable Valve Array Biochips
Author	Genggeng Liu, *Yuqin Zeng, Yuhan Zhu, Huayang Cai, Wenzhong Guo (Fuzhou Univ., China), Zipeng Li (Silicon Engineering Group, Apple, Cupertino, CA, USA), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Xing Huang (Northwestern Polytechnical Univ., China)
Page	pp. 592 - 597
Detailed information (abstract, keywords, etc)
Slides

6B-3 (Time: 15:50 - 16:15)

Title	The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic
Author	*Jan Drewniok, Marcel Walter (Tech. Univ. of Munich, Germany), Robert Wille (Technical Univ. of Munich/Software Competence Center Hagenberg GmbH, Germany)
Page	pp. 598 - 603
Detailed information (abstract, keywords, etc)
Slides

Best Paper Candidate
6B-4 (Time: 16:15 - 16:40)

Title	Towards Multiphase Clocking in Single-Flux Quantum Systems
Author	*Rassul Bairamkulov, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 604 - 609
Detailed information (abstract, keywords, etc)

6B-5 (Time: 16:40 - 17:05)

Title	Algebraic and Boolean Methods for SFQ Superconducting Circuits
Author	*Alessandro Tempia Calvino, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 610 - 615
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6C New Advances in Logic Locking and Side-Channel Analysis
Time: 15:00 - 17:05, Wednesday, January 24, 2024
Location: Room 206
Chair: Andy Yu-Guang Chen (National Central Univ., Taiwan)

6C-1 (Time: 15:00 - 15:25)

Title	LOOPLock 3.0: A Robust Cyclic Logic Locking Approach
Author	Pei-Pei Chen, Xiang-Min Yang, *Yu-Cheng He (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Yi-Ting Li, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 616 - 621
Detailed information (abstract, keywords, etc)
Slides

6C-2 (Time: 15:25 - 15:50)

Title	Logic Locking over TFHE for Securing User Data and Algorithms
Author	*Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto (Kyoto Univ., Japan)
Page	pp. 622 - 627
Detailed information (abstract, keywords, etc)

6C-3 (Time: 15:50 - 16:15)

Title	LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking
Author	Yeganeh Aghamohammadi (Univ. of California, Santa Barbara, USA), *Amin Rezaei (California State Univ., Long Beach, USA)
Page	pp. 628 - 633
Detailed information (abstract, keywords, etc)
Slides

6C-4 (Time: 16:15 - 16:40)

Title	Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars
Author	*Brojogopal Sapui, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 634 - 639
Detailed information (abstract, keywords, etc)
Slides

6C-5 (Time: 16:40 - 17:05)

Title	Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits
Author	*Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ., Japan)
Page	pp. 640 - 646
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6D Advanced Simulation and Modeling
Time: 15:00 - 17:05, Wednesday, January 24, 2024
Location: Room 207
Chairs: Zhou Jin (China Univ. of Petroleum-Beijing, China), Xueqing Li (Tsinghua Univ., China)

Best Paper Award
6D-1 (Time: 15:00 - 15:25)

Title	SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation
Author	*Xiao Dong, Songyu Sun, Yangfan Jiang (Zhejiang Univ., China), Jingtong Hu (Univ. of Pittsburgh, USA), Dawei Gao (Zhejiang Univ./Zhejiang ICsprout Semiconductor, China), Cheng Zhuo (Zhejiang Univ./Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, China)
Page	pp. 647 - 652
Detailed information (abstract, keywords, etc)

6D-2 (Time: 15:25 - 15:50)

Title	Nested Dissection Based Parallel Transient Power Grid Analysis on Public Cloud Virtual Machines
Author	*Jiawen Cheng, Zhiqiang Liu, Lingjie Li, Wenjian Yu (Tsinghua Univ., China)
Page	pp. 653 - 659
Detailed information (abstract, keywords, etc)
Slides

6D-3 (Time: 15:50 - 16:15)

Title	Efficient Sublogic-Cone-Based Switching Activity Estimation using Correlation Factor
Author	*Kexin Zhu (Tongji Univ., China), Runjie Zhang (Phlexing, China), Qing He (Tongji Univ., China)
Page	pp. 660 - 665
Detailed information (abstract, keywords, etc)
Slides

6D-4 (Time: 16:15 - 16:40)

Title	ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning
Author	*Hyunsu Chae, Keren Zhu (Univ. of Texas, Austin, USA), Bhyrav Mutnury (Dell Infrastructure Solutions Group, USA), Zixuan Jiang (Univ. of Texas, Austin, USA), Daniel de Araujo (Siemens EDA, USA), Douglas Wallace, Douglas Winterberg (Dell Infrastructure Solutions Group, USA), Adam Klivans, David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 666 - 672
Detailed information (abstract, keywords, etc)
Slides

6D-5 (Time: 16:40 - 17:05)

Title	Physics-Informed Learning for EPG-Based TDDB Assessment
Author	Dinghao Chen, *Wenjie Zhu, Xiaoman Yang, Pengpeng Ren, Zhigang Ji, Hai-Bao Chen (Shanghai Jiao Tong Univ., China)
Page	pp. 673 - 678
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6E (SS-4) Cutting-Edge Techniques for EDA in Analog/Mixed-Signal ICs
Time: 15:00 - 16:40, Wednesday, January 24, 2024
Location: Room 107/108
Chairs: Keren Zhu (Chinese Univ. of Hong Kong, Hong Kong), Zhaori Bi (Fudan Univ.)

6E-1 (Time: 15:00 - 15:25)

Title	(Invited Paper) Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches
Author	Supriyo Maji (Univ. of Texas, Austin, USA), Ahmet F. Budak (Univ. of Texas, Austin/Analog Devices, USA), Souradip Poddar, *David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 679 - 686
Detailed information (abstract, keywords, etc)

6E-2 (Time: 15:25 - 15:50)

Title	(Invited Paper) Reinforcing the Connection between Analog Design and EDA
Author	Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, Ramprasath S, Arvind K. Sharma, Ramesh Harjani, *Sachin S. Sapatnekar (Univ. of Minnesota, USA)
Page	pp. 687 - 692
Detailed information (abstract, keywords, etc)
Slides

6E-3 (Time: 15:50 - 16:15)

Title	(Invited Paper) A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation
Author	*Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi (Fudan Univ., China), Keren Zhu (Chinese Univ. of Hong Kong, China), Fan Yang, Changhao Yan (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China)
Page	pp. 693 - 700
Detailed information (abstract, keywords, etc)
Slides

6E-4 (Time: 16:15 - 16:40)

Title	(Invited Paper) Performance-Driven Analog Layout Automation: Current Status and Future Directions
Author	Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, *Keren Zhu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 701 - 707
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 3K Keynote Session III
Time: 18:15 - 19:15, Wednesday, January 24, 2024
Location: Grand Ballroom A/B
Chairs: Kyu-Myung Choi (Seoul National Univ., Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea)

3K-1 (Time: 18:15 - 19:15)

Title	(Keynote Address) AI/ML and EDA: Current Status and Perspectives on the Future
Author	Andrew B. Kahng (Univ. of California San Diego, USA)
Detailed information (abstract, etc)

Thursday, January 25, 2024

[To Session Table]

Session 7A System Performance and Debugging
Time: 9:00 - 10:15, Thursday, January 25, 2024
Location: Room 204
Chairs: Jing-Jia Liou (National Tsing Hua Univ., Taiwan), Shigeru Yamashita (Ritsumeikan Univ., Japan)

Best Paper Candidate
7A-1 (Time: 9:00 - 9:25)

Title	The Optimal Quantum of Temporal Decoupling
Author	*Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach (RWTH Aachen Univ., Germany), Lukas Jünger (MachineWare GmbH, Germany), Rainer Leupers (RWTH Aachen Univ., Germany)
Page	pp. 708 - 713
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 9:25 - 9:50)

Title	Towards a Highly Interactive Design-Debug-Verification Cycle
Author	*Lucas Klemmer, Daniel Groβe (Johannes Kepler Univ. Linz, Austria)
Page	pp. 714 - 719
Detailed information (abstract, keywords, etc)

7A-3 (Time: 9:50 - 10:15)

Title	Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation
Author	Hsuan-Yi Lin, *Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 720 - 725
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7B Innovations in Autonomous Systems: Hyperdimensional Computing and Emerging Application Frontiers
Time: 9:00 - 10:15, Thursday, January 25, 2024
Location: Room 205
Chair: Takashi Sato (Kyoto Univ., Japan)

7B-1 (Time: 9:00 - 9:25)

Title	BoostIID: Fault-agnostic Online Detection of WCET Changes in Autonomous Driving
Author	*Saehanseul Yi, Nikil Dutt (Univ. of California, Irvine, USA)
Page	pp. 726 - 731
Detailed information (abstract, keywords, etc)
Slides

7B-2 (Time: 9:25 - 9:50)

Title	KalmanHD: Robust On-Device Time Series Forecasting with Hyperdimensional Computing
Author	*Ivannia Gomez Moreno (CETYS Univ. Campus Tijuana, Mexico), Xiaofan Yu, Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 732 - 737
Detailed information (abstract, keywords, etc)
Slides

7B-3 (Time: 9:50 - 10:15)

Title	HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing
Author	*Haomin Li, Fangxin Liu (Shanghai Jiao Tong Univ., China), Yichi Chen (Tianjin Univ., China), Li Jiang (Shanghai Jiao Tong Univ., China)
Page	pp. 738 - 743
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7C Productivity Management for High Level Design
Time: 9:00 - 10:15, Thursday, January 25, 2024
Location: Room 206
Chair: Kenshu Seto (Kumamoto Univ., Japan)

7C-1 (Time: 9:00 - 9:25)

Title	RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Author	*Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 744 - 749
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 9:25 - 9:50)

Title	LSTP : A Logic Synthesis Timing Predictor
Author	*Haisheng Zheng (Shanghai AI Laboratory, China), Zhuolun He, Fangzhou Liu, Zehua Pei (Shanghai AI Laboratory/Chinese Univ. of Hong Kong, Hong Kong), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 750 - 755
Detailed information (abstract, keywords, etc)
Slides

7C-3 (Time: 9:50 - 10:15)

Title	Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs
Author	*Alex Chan (Newcastle Univ., UK), Danil Sokolov, Victor Khomenko (Dialog Semiconductor (Renasas), UK), Alex Yakovlev (Newcastle Univ., UK)
Page	pp. 756 - 761
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7D Emerging Memory Yield Optimization and Modeling
Time: 9:00 - 10:15, Thursday, January 25, 2024
Location: Room 207
Chair: Jun Shiomi (Osaka Univ.)

7D-1 (Time: 9:00 - 9:25)

Title	Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery
Author	Anurup Saha, Chandramouli Amarnath, *Kwondo Ma, Abhijit Chatterjee (Georgia Tech, USA)
Page	pp. 762 - 767
Detailed information (abstract, keywords, etc)
Slides

7D-2 (Time: 9:25 - 9:50)

Title	Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation
Author	*Tianshu Hou (Shanghai Jiao Tong Univ., China), Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang (Univ. of Hong Kong, Hong Kong), Hai-Bao Chen (Shanghai Jiao Tong Univ., China), Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 768 - 773
Detailed information (abstract, keywords, etc)

7D-3 (Time: 9:50 - 10:15)

Title	Hard Error Correction in STT-MRAM
Author	*Surendra Hemaram, Mehdi B Tahoori (Karlsruhe Inst. of Tech. (KIT), Germany), Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar (IMEC, Belgium)
Page	pp. 774 - 779
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7E (SS-5) Enabling Chiplet-based Custom Designs
Time: 8:35 - 10:15, Thursday, January 25, 2024
Location: Room 107/108
Chairs: Antonino Tumeo (Pacific Northwest National Laboratory), Yi Zhou (Univ. of Utah), Yu Cao (Univ. of Minnesota)

7E-1 (Time: 8:35 - 9:00)

Title	(Invited Paper) Exploiting 2.5D/3D Heterogeneous Integration for AI Computing
Author	Zhenyu Wang, Jingbo Sun (Arizona State Univ., USA), Alper Goksoy (Univ. of Wisconsin-Madison, USA), Sumit Kumar Mandal (Indian Institute of Science, India), Yaotian Liu (Arizona State Univ., USA), Jae-sun Seo (Cornell Tech, USA), Chaitali Chakrabarti (Arizona State Univ., USA), Umit Y. Ogras (Univ. of Wisconsin-Madison, USA), Vidya Chhabria, Jeff Zhang (Arizona State Univ., USA), *Yu Cao (Univ. of Minnesota, USA)
Page	pp. 780 - 786
Detailed information (abstract, keywords, etc)
Slides

7E-2 (Time: 9:00 - 9:25)

Title	(Invited Paper) Challenges and Opportunities to Enable Large-scale Computing via Heterogeneous Chiplets
Author	Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang (Univ. of Pittsburgh, USA), *Weifeng Zhang (Lightelligence Inc, USA), Dharmesh Jani (Meta, USA), Peipei Zhou (Univ. of Pittsburgh, USA)
Page	pp. 787 - 792
Detailed information (abstract, keywords, etc)
Slides

7E-3 (Time: 9:25 - 9:50)

Title	(Invited Paper) Heterogeneous Microelectronics Codesign for Edge Sensing at Deep Cryogenic Temperatures
Author	Jeff Fredenburg (Fermilab, USA)
Detailed information

7E-4 (Time: 9:50 - 10:15)

Title	(Invited Paper) Towards Automated Generation of Chiplet-Based System
Author	*Ankur Limaye, Claudio Barone, Nicolas Bohm Agostini, Marco Minutoli, Joseph Manzano, Vito Giovanni Castellana (Pacific Northwest National Laboratory, USA), Giovanni Gozzi, Michele Fiorito, Serena Curzel (Politecnico di Milano, Italy), Fabrizio Ferrandi (Politecnico di Milano, USA), Antonino Tumeo (Pacific Northwest National Laboratory, USA)
Page	pp. 793 - 798
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4K Keynote Session IV
Time: 10:30 - 11:30, Thursday, January 25, 2024
Location: Room Premier A/B
Chairs: Kyu-Myung Choi (Seoul National Univ., Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea)

4K-1

Title	(Keynote Address) Unleashing the Future of IC Design with AI Innovation
Author	Erick Chao (Cadence Design Systems, Taiwan)
Detailed information (abstract, etc)

[To Session Table]

Session 8A Advances in Efficient Embedded Computing: from Hardware Accelerator to Task Management
Time: 13:00 - 14:40, Thursday, January 25, 2024
Location: Room 204
Chair: Sharad Malik (Princeton Univ., USA)

8A-1 (Time: 13:00 - 13:25)

Title	Flexible Spatio-Temporal Energy-Efficient Runtime Management
Author	*Robert Khasanov, Marc Dietrich, Jeronimo Castrillon (TU Dresden, Germany)
Page	pp. 799 - 806
Detailed information (abstract, keywords, etc)
Slides

8A-2 (Time: 13:25 - 13:50)

Title	Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Author	*Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Inst. of Tech., Japan)
Page	pp. 807 - 813
Detailed information (abstract, keywords, etc)
Slides

8A-3 (Time: 13:50 - 14:15)

Title	Meeting Job-Level Dependencies by Task Merging
Author	*Matthias Becker (Royal Inst. of Tech., Sweden)
Page	pp. 814 - 820
Detailed information (abstract, keywords, etc)
Slides

8A-4 (Time: 14:15 - 14:40)

Title	A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators
Author	*Xuchen Gao, Yunhui Qiu, Yuan Dai, Wenbo Yin, Lingli Wang (Fudan Univ., China)
Page	pp. 821 - 826
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8B In-Memory Computing Architecture Design and Logic Synthesis
Time: 13:00 - 14:40, Thursday, January 25, 2024
Location: Room 205
Chair: Shuo-Han Chen (National Yang Ming Chiao Tung Univ., Taiwan)

8B-1 (Time: 13:00 - 13:25)

Title	LOSSS- Logic Synthesis based on Several Stateful logic gates for high time-efficient computing
Author	Yihong Hu (National Univ. of Defense Tech., China), *Nuo Xu, Chaochao Feng (National Univ. of Defense Tech./Key Laboratory of Advanced Microprocessor Chips and Systems, China), Wei Tong (Huazhong Univ. of Science and Tech., China), Kang Liu, Liang Fang (National Univ. of Defense Tech., China)
Page	pp. 827 - 833
Detailed information (abstract, keywords, etc)
Slides

8B-2 (Time: 13:25 - 13:50)

Title	Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms
Author	Sven Thijssen, *Muhammad Rashedul Haq Rashed, Hao Zheng (Univ. of Central Florida, USA), Sumit Kumar Jha (Florida International Univ., USA), Rickard Ewetz (Univ. of Central Florida, USA)
Page	pp. 834 - 839
Detailed information (abstract, keywords, etc)

8B-3 (Time: 13:50 - 14:15)

Title	READ-based In-Memory Computing using Sentential Decision Diagrams
Author	Sven Thijssen, *Muhammad Rashedul Haq Rashed (Univ. of Central Florida, USA), Sumit Kumar Jha (Florida International Univ., USA), Rickard Ewetz (Univ. of Central Florida, USA)
Page	pp. 840 - 845
Detailed information (abstract, keywords, etc)

8B-4 (Time: 14:15 - 14:40)

Title	ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow
Author	*Liang Zhao, Yu Qian, Fanzi Meng, Xiapeng Xu, Xunzhao Yin, Cheng Zhuo (Zhejiang Univ., China)
Page	pp. 846 - 851
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8C Firing Less for Evolution: Quantization & Learning Spikes
Time: 13:00 - 14:40, Thursday, January 25, 2024
Location: Room 206
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

Best Paper Candidate
8C-1 (Time: 13:00 - 13:25)

Title	MINT: Multiplier-less Integer Quantization for Energy Efficient Spiking Neural Networks
Author	*Ruokai Yin, Yuhang Li, Abhishek Moitra, Priyadarshini Panda (Yale Univ., USA)
Page	pp. 852 - 857
Detailed information (abstract, keywords, etc)
Slides

8C-2 (Time: 13:25 - 13:50)

Title	TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron
Author	*Yuxuan Yang, Zihao Xuan, Yi Kang (Univ. of Science and Tech. of China, China)
Page	pp. 858 - 863
Detailed information (abstract, keywords, etc)
Slides

8C-3 (Time: 13:50 - 14:15)

Title	TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks
Author	*Fangxin Liu, Haomin Li, Ning Yang, Zongwu Wang (Shanghai Jiao Tong Univ., China), Tao Yang (Huawei Technologies, China), Li Jiang (Shanghai Jiao Tong Univ., China)
Page	pp. 864 - 869
Detailed information (abstract, keywords, etc)
Slides

8C-4 (Time: 14:15 - 14:40)

Title	SOLSA: Neuromorphic Spatiotemporal Online Learning for Synaptic Adaptation
Author	Zhenhang Zhang, Jingang Jin, Haowen Fang, *Qinru Qiu (Syracuse Univ., USA)
Page	pp. 870 - 875
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8D New Techniques for Photonics and Analog Circuit Design
Time: 13:00 - 14:40, Thursday, January 25, 2024
Location: Room 207
Chairs: Yuanqing Chen (Beihang Univ., China), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

8D-1 (Time: 13:00 - 13:25)

Title	Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams
Author	*Raphael Cardoso, Clément Zrounba (Institut des Nanotechnologies de Lyon, France), Mohab Abdalla (RMIT Univ., France), Paul Jimenez, Mauricio Gomes de Queiroz (Institut des Nanotechnologies de Lyon, France), Benoît Charbonnier (Univ. Grenoble Alpes/CEA LETI, France), Fabio Pavanello (Institut des Nanotechnologies de Lyon/Univ. Grenoble Alpes/Univ. Savoie Mont Blanc, France), Ian O'Connor (Institut des Nanotechnologies de Lyon, France), Sébastien Le Beux (Univ. of Concordia, Canada)
Page	pp. 876 - 881
Detailed information (abstract, keywords, etc)
Slides

8D-2 (Time: 13:25 - 13:50)

Title	An Efficient Branch-and-Bound Routing Algorithm for Optical NoCs
Author	*Yihao Liu, Yaoyao Ye (Shanghai Jiao Tong Univ., China)
Page	pp. 882 - 887
Detailed information (abstract, keywords, etc)
Slides

8D-3 (Time: 13:50 - 14:15)

Title	Boosting Graph Spectral Sparsification via Parallel Sparse Approximate Inverse of Cholesky Factor
Author	*Baiyu Chen, Zhiqiang Liu, Yibin Zhang, Wenjian Yu (Tsinghua Univ., China)
Page	pp. 888 - 893
Detailed information (abstract, keywords, etc)
Slides

8D-4 (Time: 14:15 - 14:40)

Title	Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing
Author	*Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China)
Page	pp. 894 - 899
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8E (JW-1) TILOS & AI-EDA Joint Workshop - I
Time: 13:00 - 14:40, Thursday, January 25, 2024
Location: Room 107/108
Chair: Kyumyung Choi (Seoul National Univ., Republic of Korea)

8E-1 (Time: 13:00 - 13:25)

Title	(Joint Workshop) Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors
Author	Jeong-taek Kong, SoYoung Kim (Sungkyunkwan Univ., Republic of Korea)
Detailed information

8E-2 (Time: 13:25 - 13:50)

Title	(Joint Workshop) Fast Timing/Power Library Generation Using Machine Learning
Author	Daijoon Hyun (Sejong Univ., Republic of Korea)
Detailed information

8E-3 (Time: 13:50 - 14:15)

Title	(Joint Workshop) Clustering-Based Methodology for Fast and Improved Placement of Large-Scale Designs
Author	Andrew Kahng (UCSD, USA)
Detailed information

8E-4 (Time: 14:15 - 14:40)

Title	(Joint Workshop) Routability Prediction and Optimization Using Machine Learning Techniques
Author	Seokhyeong Kang (POSTECH, Republic of Korea)
Detailed information

[To Session Table]

Session 9A Advancing AI Algorithms: Faster, Smarter, and More Efficient
Time: 15:00 - 16:40, Thursday, January 25, 2024
Location: Room 204
Chairs: Yu Wang (Tsinghua Univ., China), Li Jiang (Shanghai Jiao Tong Univ., China)

9A-1 (Time: 15:00 - 15:25)

Title	Quantization-aware Optimization Approach for CNNs Inference on CPUs
Author	*Jiasong Chen, Zeming Xie, Weipeng Liang, Bosheng Liu, Xin Zheng, Jigang Wu, Xiaoming Xiong (Guangdong Univ. of Tech., China)
Page	pp. 900 - 905
Detailed information (abstract, keywords, etc)

9A-2 (Time: 15:25 - 15:50)

Title	TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation
Author	*Shiyuan Huang, Fangxin Liu (Shanghai Jiao Tong Univ., China), Tian Li (Huawei Technologies, China), Zongwu Wang, Haomin Li, Li Jiang (Shanghai Jiao Tong Univ., China)
Page	pp. 906 - 911
Detailed information (abstract, keywords, etc)

9A-3 (Time: 15:50 - 16:15)

Title	An automated approach for improving the inference latency and energy efficiency of pretrained CNNs by removing irrelevant pixels with focused convolutions
Author	Caleb Tung, Nicholas Eliopoulos, Purvish Jajal, Gowri Ramshankar, Chen-Yun Yang (Purdue Univ., USA), Nicholas Synovic (Loyola Univ. Chicago, USA), Xuecen Zhang, Vipin Chaudhary (Case Western Reserve Univ., USA), *George K. Thiruvathukal (Loyola Univ. Chicago, USA), Yung-Hsiang Lu (Purdue Univ., USA)
Page	pp. 912 - 917
Detailed information (abstract, keywords, etc)

9A-4 (Time: 16:15 - 16:40)

Title	PIONEER: Highly Efficient and Accurate Hyperdimensional Computing using Learned Projection
Author	*Fatemeh Asgarinejad (Univ. of California San Diego/San Diego State Univ., USA), Justin Morris (California State Univ. San Marcos, USA), Tajana Rosing (Univ. of California San Diego, USA), Baris Aksanli (San Diego State Univ., USA)
Page	pp. 918 - 923
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9B Design Explorations for Neural Network Accelerators
Time: 15:00 - 17:05, Thursday, January 25, 2024
Location: Room 205
Chair: Chun-Yi Lee (National Tsing Hua Univ., Taiwan)

9B-1 (Time: 15:00 - 15:25)

Title	Logic Design of Neural Networks for High-Throughput and Low-Power Applications
Author	*Kangwei Xu (Tech. Univ. of Munich, Germany), Grace Li Zhang (Technical Univ. of Darmstadt, Germany), Ulf Schlichtmann, Bing Li (Tech. Univ. of Munich, Germany)
Page	pp. 924 - 929
Detailed information (abstract, keywords, etc)
Slides

9B-2 (Time: 15:25 - 15:50)

Title	Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators
Author	Yi Li, Aarti Gupta, *Sharad Malik (Princeton Univ., USA)
Page	pp. 930 - 936
Detailed information (abstract, keywords, etc)
Slides

9B-3 (Time: 15:50 - 16:15)

Title	Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication
Author	*Priscilla Sharon Allwin, Manil Dev Gomony, Marc Geilen (Eindhoven Univ. of Tech., Netherlands)
Page	pp. 937 - 942
Detailed information (abstract, keywords, etc)
Slides

9B-4 (Time: 16:15 - 16:40)

Title	PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion
Author	Xilang Zhou, *Shuyang Li (Fudan Univ., China), Haodong Lu (Nanjing Univ. of Posts and Telecommunications, China), Kun Wang (Fudan Univ., China)
Page	pp. 943 - 948
Detailed information (abstract, keywords, etc)
Slides

9B-5 (Time: 16:40 - 17:05)

Title	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge
Author	*Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang (Nanjing Univ., China)
Page	pp. 949 - 954
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9C High-Level Security Verification and Efficient Implementation
Time: 15:00 - 17:05, Thursday, January 25, 2024
Location: Room 206
Chairs: Amin Rezaei (California State Univ., Long Beach, USA), Danella Zhao (Univ. of Arizona, USA)

9C-1 (Time: 15:00 - 15:25)

Title	Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective
Author	Zhaoxiang Liu, Kejun Chen (Kansas State Univ., USA), Dean Sullivan (Univ. of New Hampshire, USA), Orlando Arias (Univ. of Massachusetts Lowel, USA), Raj Dutta (Silicon Assurance, USA), *Yier Jin (Univ. of Science and Tech. of China, USA), Xiaolong Guo (Kansas State Univ., USA)
Page	pp. 955 - 960
Detailed information (abstract, keywords, etc)

9C-2 (Time: 15:25 - 15:50)

Title	d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems
Author	Garett Cunningham, Harsha Chenji, *David Juedes, Avinash Karanth (Ohio Univ., USA)
Page	pp. 961 - 966
Detailed information (abstract, keywords, etc)
Slides

9C-3 (Time: 15:50 - 16:15)

Title	Security Coverage Metrics for Information Flow at the System Level
Author	*Ece Nur Demirhan Coşkun (DFKI GmbH, Germany), Sallar Ahmadi-Pour (Univ. of Bremen, Germany), Muhammad Hassan, Rolf Drechsler (Univ. of Bremen/DFKI GmbH, Germany)
Page	pp. 967 - 972
Detailed information (abstract, keywords, etc)
Slides

9C-4 (Time: 16:15 - 16:40)

Title	Theoretical Patchability Quantification for IP-Level Hardware Patching Designs
Author	*Wei-Kai Liu (Duke Univ., USA), Benjamin Tan (Univ. of Calgary, Canada), Jason M. Fung (Intel, USA), Krishnendu Chakrabarty (Arizona State Univ., USA)
Page	pp. 973 - 978
Detailed information (abstract, keywords, etc)
Slides

9C-5 (Time: 16:40 - 17:05)

Title	Multiplierless Design of High-Speed Very Large Constant Multiplications
Author	*Levent Aksoy (Tallinn Univ. of Tech., Estonia), Debapriya Basu Roy (Indian Inst. of Tech. Kanpur, India), Malik Imran, Samuel Pagliarini (Tallinn Univ. of Tech., Estonia)
Page	pp. 979 - 984
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9D Routing
Time: 15:00 - 16:15, Thursday, January 25, 2024
Location: Room 207
Chair: Masato Inagi (Hiroshima City Univ., Japan)

9D-1 (Time: 15:00 - 15:25)

Title	V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting
Author	*Ping Zhang, Pengju Yao (Fuzhou Univ., China), Xingquan Li (Pengcheng Laboratory, China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Wenxing Zhu (Fuzhou Univ., China)
Page	pp. 985 - 990
Detailed information (abstract, keywords, etc)
Slides

9D-2 (Time: 15:25 - 15:50)

Title	A Fast and Robust Global Router with Capacity Reduction Techniques
Author	*Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 991 - 996
Detailed information (abstract, keywords, etc)

9D-3 (Time: 15:50 - 16:15)

Title	A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides
Author	Zhongdong Qi, *Shizhe Hu, Qi Peng, Hailong You, Chao Han, Zhangming Zhu (Xidian Univ., China)
Page	pp. 997 - 1002
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9E (JW-2) TILOS & AI-EDA Joint Workshop - II
Time: 15:00 - 16:40, Thursday, January 25, 2024
Location: Room 107/108
Chair: Youngsoo Shin (KAIST, Republic of Korea)

9E-1 (Time: 15:00 - 15:25)

Title	(Joint Workshop) ML Assisted DTCO Framework & Physical Design Optimization using DSO
Author	Kyumyung Choi, Taewhan Kim (Seoul National Univ., Republic of Korea)
Detailed information

9E-2 (Time: 15:25 - 15:50)

Title	(Joint Workshop) Differential Design Search: A Learning-Based Optimization Framework for EDA
Author	Jaeyong Jung (Incheon National Univ., Republic of Korea)
Detailed information

9E-3 (Time: 15:50 - 16:15)

Title	(Joint Workshop) AI-Based Design Optimization of SRAM-MRAM Hybrid Cache and On-Chip Interconnection Network
Author	Eui-young Chung (Yonsei Univ., Republic of Korea)
Detailed information

9E-4 (Time: 16:15 - 16:40)

Title	(Joint Workshop) ML/AI and Cross Layer Optimizations for Electronic and Photonic Design Automation
Author	David Pan (Univ. of Texas, Austin, USA)
Detailed information

The 29th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 29th Asia and South Pacific Design Automation Conference
Technical Program