Keynote Addresses

Opening & KeynoteⅠ: Tuesday, January 23

Advanced Technology and Design Enablement

Sei Seung Yoon (EVP, Design Enablement (Samsung Foundry))

Samsung Electronics, Korea

Abstract:
Next gen SoC designs are witnessing remarkable advancements in MBCFET, library design, migration to advanced nodes, automotive design, and Multi Die Integration (MDI). Improving fundamental technologies helps achieve high performance computing with continuous pitch scaling requirements. Focusing on this aspect, Samsung Foundry pioneered in applying MBCFET for it’s designs. The MBCFET is an innovative CMOS structure that provides power-performance advantage over FinFET through key device characteristics. Newly suggested low-area standard cell architecture, EG-less design solution, and DTCO also make this possible. EASY migration and library design methodologies enable mature IP designs on the advanced node, thus reducing the development time. To meet the ever growing needs of Automotive Design, Samsung Foundry is working towards an Auto Grade IP Design and Design Solution. To offer superior packaging solutions, Samsung Foundry is focusing on MDI technologies beyond the existing 2D technologies. As a part of our efforts to complete and mature advanced technologies in the semiconductor industry, we are collaborating with numerous EDA companies.

Biography:
Sei Seung Yoon currently heads the Design Enablement Team in Samsung Foundry, Samsung Electronics, as the Executive Vice President and Team Leader. He graduated from Yonsei University, South Korea, in 1988. His vast experience in the semiconductor industry spans over 30+ years, across companies such as Qualcomm, Micron Technology, and Samsung. In Samsung Foundry, his current focus lies in developing technologies for future nodes such as GAA architecture definition and technology enablement. He has played key roles in developing advanced technologies across multiple sectors.

KeynoteⅡ: Wednesday, January 24

Present and Future Challenges of High-Bandwidth Memory

Myeong-Jae Park (VP, Leading Product Design)

SK hynix, Korea

Abstract:
HBM(High-Bandwidth Memory) is the best-performing memory product that is used in high-end computing systems such as supercomputers and AI accelerators. The recent boom in machine learning is due in part to the development of computing technologies where HBM, the fastest DRAM played a key role in overcoming the performance limitations. In order to achieve high bandwidth of HBM, various technologies and sophisticated design techniques are required. Especially, the complex structure of stacking a single logic die with 4 to 16 DRAM dies also makes its development more challenging. Since SK hynix developed its first HBM product in 2015, five generations of HBM products have been developed over the past 9 years, and discussions are underway for the development of HBM4, which corresponds to the 6th generation. During this period, bandwidth has increased by 12 times and power efficiency has improved by 3-fold. These performance improvements have been made possible due to various design and process innovations, and given the rapid progress in AI technology, the continuous improvement of high-end memory products like HBM is essential. However, HBM is now facing various technical challenges. Increasing bandwidth, power, and capacity on a small interposer is reaching its technical limits, and issues such as thermal and reliability are becoming more serious. This keynote will present a broad overview of the latest developments in HBM including the current technical challenges from design to devices and packaging technologies, and present future directions for HBM’s developments. Memory solutions beyond HBM, such as PiM and 3D solutions will also be covered.

Biography:
Myeong-Jae Park received the B.S., M.S., and Ph.D. degrees from Seoul National University, Seoul, South Korea, in 2003, 2006, and 2014, respectively. He joined SK hynix, Icheon, Korea in 2014 where he led the design of HBM2E, HBM3 and HBM3E. He is currently in charge of the Advanced DRAM Product Design division as the vice president. Prior to joining SK hynix, Dr. Park was with Anapass, Inc., Seoul, Korea as Principal Engineer from 2006 to 2010 where he invented AiPi(Advanced intra-panel interface). His research interests include 3D-DRAM, low-power mixed signal systems and their design methodologies.

Keynote Ⅲ: Wednesday, January 24

AI/ML and EDA: Current Status and Perspectives on the Future

Andrew B. Kahng (Distinguished Professor of CSE and ECE)

University of California San Diego

Abstract:
In the six years since an ASP-DAC 2018 invited talk on “New Directions for Learning-Based IC Design Tools and Methodologies”, much has changed. Today, more than half of the research papers at leading EDA conferences involve applications of machine learning. Deep learning approaches have been claimed to achieve superhuman design outcomes. Infusion of AI/ML is seen in all facets of EDA, including the product offerings of the major EDA vendors. The latest wave: large language models and generative AI, everywhere. What will the next six years bring before we meet again at ASP-DAC 2030?
This talk will reflect on the current status of AI/ML and EDA: (1) surprises and disappointments, (2) clearer understanding of where AI/ML can and cannot (yet) move the needle, and (3) fundamental challenges and needs. Some perspectives on the future will also be given, including: (1) newly low-hanging fruits, (2) oncoming singularities, and (3) how research, teaching and R&D in our field might evolve.

Biography:
Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He was the 2019 Ho-Am Prize laureate in Engineering. He has served as general chair of DAC, ISPD and other conferences, and from 2000-2016 served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He has been principal investigator of “OpenROAD” (https://theopenroadproject.org/) since June 2018, and until August 2023 served as principal investigator and director of “TILOS” (https://tilos.ai/), a U.S. NSF AI Research Institute

Keynote Ⅳ: Thursday, January 25

Unleashing the Future of IC Design with AI Innovation

Erick Chao (Senior Software Architect, Digital and Signoff Group)

Cadence Design Systems, Taiwan

Abstract:
The integration of AI into electronic design holds the potential to revolutionize the industry by enabling innovative and efficient chip design processes. Cadence, a leading provider of electronic design automation (EDA) tools and services, has deployed AI into its chip and system design tools to enable customers to harness its transformative capabilities. In this talk we will share the ways in which Cadence is leveraging AI in chip design.

Biography:
Erick's background in IC design, chip implementation, and EDA development, spanning over two decades, has equipped him with a deep understanding of user requirements and software development within the Electronic Design Automation (EDA) field. At MediaTek as deputy director in CPU design division, he worked with team for many generations of application processors in mobile fragment. At Cadence Design Systems as senior director, Erick is likely to have a broad perspective that encompasses various aspects of EDA. This perspective ranges from that of an adept end-user who understands the practical needs and challenges faced by EDA professionals to that of a contributor to EDA solution development, particularly leveraging AI and machine learning (ML) technologies. Erick earned his M.S. from University of National Yang Ming Chiao Tung in Taiwan.